The present invention relates to a technology for improving the number of rewrite assurances for a non-volatile memory, for example, a technology effective for application to a microcomputer with an electrically erasable and programmable flash memory built therein.
An electrically erasable and programmable non-volatile memory (hereinafter also called simply “flash memory”) such as a flash memory or the like stores information according to the difference between threshold voltages programmed to memory cells. The difference between the threshold voltages is obtained according to the difference between the values or amounts of electrons or positive holes held in a floating gate. The performance of holding the electrons or positive holes in the flash memory is degraded with an increase in the number of rewritings. Accordingly, the number of rewrite assurances finite for the use of the flash memory is normally taken into consideration from the viewpoint of the reliability of stored information.
In order to allow the number of rewritings exceeding the number of rewrite assurances corresponding to about 100 times, for example, storage areas of the flash memory are successively switched and controlled every number of rewritings corresponding to 100 times, thereby making it possible to cope with it. To this end, a large storage capacity reaching several tens of times to several thousand of times the actually-used capacity is needed.
In order to improve or increase the number of assurances for the rewriting of the flash memory, a gate oxide film can be rendered thick to enhance the performance of holding electrons or positive holes as a device-based method. Further, an ECC (Error Check and Correct) circuit can be adopted as a circuitry method or approach. A technology in which ECC is applied to an EEPROM built in a one-chip type microcomputer, has been shown in Unexamined Patent Publication No. Hei 11(1999)-296392.
An erasable and programmable non-volatile memory such as a flash memory performs information storage according to a threshold voltage corresponding to the amount of electrons or positive holes injected into a floating gate of each memory cell. A threshold voltage characteristic of such a memory cell is degraded with time according to an increase in the number of rewritings, etc. As the degradation in characteristic advances or continues, the probability that a writing error will occur upon a verify operation at data rewriting. Thus, as writing/erasing for the flash memory is repeatedly done, its characteristic is deteriorated and “spoiled bits” that information cannot be held normally, are generated. The number of rewritings assured by the flash memory or the on-chip type microcomputer using the same is limited by the degradation in characteristic. As methods of increasing or improving the number of rewritings, the following technologies have heretofore been known.
The first technology is a method or technique implemented as a circuit structure of a flash memory. It is configured in such a manner that for instance, the same bit information is written into two (a plurality of cells in general) cells upon writing, whereas upon reading, data are read from both memory cells, and if at least one is kept in a high threshold state, then data of a logical value corresponding to the high threshold state is outputted. Alternatively, a circuit for a flash memory is configured in such a manner that the same bit information is written into three or more memory cells upon writing, whereas upon reading, data are read from these cells, and majority logic of the read data is taken and the result thereof is outputted. As an example of a reference having described the flash memory having such a configuration, Unexamined Patent Publication No. Hei 3(1991)-57048 is known.
The second technology is one for providing an error-correcting function block on a chip and is intended to generate a check bit upon writing and perform an error detection and correction from the original information and check bit upon reading. As an example of a reference having described the present technology, there is known 200 Symposium on VLSI Circuits Digest of Technical Papers, pp162-165.
As the third technology, there is known one wherein as described in Unexamined Patent Publication No. Hei 7(1995)-210215, when a CPU effects data writing on an EEPROM, the data writing is made to three places corresponding to two areas lying within the EEPROM and a backup memory different from the EEPROM, and data are read from the three places when the CPU performs data reading, and when the two data thereof coincide with each other, data related to the coincidence of the two is judged to be proper.